The speed of today's silicon bipolar junction transistors (BJT) with about 50 GHz f.sub.T (maximum transition frequency) is reaching its physical limitations because of the trade-off between the thickness and resistivity of the base layer. By adding some germanium into the base of a conventional BJT, the high-frequency characteristics can be improved substantially. The new device is a SiGe (silicon germanium) double HBT (heterojunction bipolar transistor) structure. The layer structure is usually grown with MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition), but it is also possible to implant Ge into the Si to achieve a similar effect but with less control of the doping profile. During the last years, SiGe HBTs have shown record high-frequency performance for silicon based devices with regards to f.sub.T and f.sub.max (maximum oscillation frequency). For high-frequency applications, e.g. wireless communication, the SiGe HBT can be used to boost performance of existing double-polysilicon HF-ICs and BiCMOS technologies.
However, a simple, yet feasible method to fabricate high-performance SiGe HBT transistors is by using blanket epitaxial deposition of the device layers, and build-up of the device structure by mesa transistor formation, similar to standard fabrication of compound semiconductor devices. The mesa structure has been widely used to quickly verify concepts and explore device characteristics because of its simplicity and ease of fabrication. Typical SiGe mesa device structure types are described in.
Circuits of IC-type generally require more complicated structures, and the basic mesa concept is not suitable for this. Also, the maximum operating supply voltage is set by the BV.sub.CBO (collector-emitter breakdown voltage) of the transistor, which is proportional to BV.sub.CBO (collector-base breakdown voltage), and .beta. (the DC current gain) of the transistor. The BV.sub.CBO is mainly set by the doping and the thickness of the collector layer. Only for low-voltage devices, the collector will be thin enough for easily making mesa structures feasible without too much topography.
High-frequency transistors were first fabricated in germanium in the late fifties but were soon replaced by silicon bipolar transistors in the beginning of the sixties, and have since then dominated the RF power area, especially for high output power levels and high supply voltages (25 V). Power transistors are especially designed to deliver high output power and high gain. Manufacturing process, device parameters, layouts and package are carefully tuned for this purpose. The devices need to meet numerous detailed requirements for breakdown voltages, DC gain or transconductance, capacitance, RF gain, ruggedness, noise figure, input/output impedance, distortion etc. The operating frequency ranges from several hundred MHz up into the GHz region. Because of the rapidly expanding telecommunications market, there is a strong driving force to further improve the existing technology, as well as to explore new types of devices.
For handheld wireless application, battery operation limits the supply voltage to the 3-6 V range. The output power ranges typically from 0.25 W up to 4 W. For maximum performance, discrete devices are used, and usually consist of one n-type device on a single die. The high output power is achieved by paralleling many transistor cells on a single die. The package may also be a module (typically a small ceramic substrate with semiconductor chips and passive components mounted on its surface, housed in one casing), and several RF power transistors dies may be used in a module.
For all types of high-frequency power transistors, a low impedance emitter/source path to ground is central for transferring the power to the load. This is true for all types of transistors, bipolar as well as FETs (field-effect transistors).
For IC-type of structures, complicated schemes are used to isolate the different device regions, e.g. well or trench isolations. Discrete bipolar devices generally have the collector as substrate, while emitter and base are contacted at the upper side of the semiconductor die using bond pads and bond wires. Only having two different types of contact at the front side ease the fabrication and connections to the device, especially for large power transistors where many transistor cells and bond wires are used.
A parasitic capacitance from metal patterns on the chip surface (base or emitter metalization) via the isolation layer to the substrate (collector) will occur. The collector-base capacitance (Miller capacitance) has a large impact on the gain and must be reduced. This can be done by using thick insulating silicon dioxide, and by using small base metalization area.